Comparator based analog-to-digital converters (ADCs), for example, ADCs with structures of successive approximation register (SAR), flash, folding and sub-ranging are always very popular research issues, and a feature thereof is that none operational amplifier (OPAMP) is used, so that a fabrication process thereof could be highly integrated, especially in application of a deep-submicron fabrication technique (<0.13 um).
And, comparators in many high-speed (>GSample/second, GS/s) ADCs generally apply a dynamic structure, so that none static current is consumed. Moreover, the comparator based ADC also has an advantage of greatly reducing power consumption of the ADC. Therefore, in recent years, the OPAMP based pipelined ADCs are developed towards a trend of the comparator based ADCs. It could be known that the comparator based ADCs gradually become one of technical focuses in research and development of related field of the disclosure, so that it is an important issue to be developed in the related field of the disclosure to achieve advantages of high-speed (>GS/s), low power consumption (milliwatt scale) and medium/high resolution (≧8 bits) of the comparator based ADCs.
Regarding the high-speed and low power consumption comparator, many related structures are disclosed, in which the most representative one is disclosed in a journal article of IEEE JSSC 1993 authored by Kobayashi et al. entitled “A current controlled latch sense amplifier and a static power-saving input buffer for low-power architecture”. Moreover, regarding the medium/high resolution comparator, a representative paper thereof is disclosed in a journal article of IEEE JSSC, 1992 authored by Razavi et al. entitled “Design techniques for high-speed, high-resolution comparators”.
According to studies after 2000, when a sampling frequency of the comparator based ADC is limited to be above GS/s, a dynamic comparator provided by Kobayashi et al. can meet the requirements of high-speed and low power consumption, so that it becomes a most popular comparator structure. However, regarding the comparator structure simultaneously satisfying the requirements of medium/high resolution, high-speed and low power consumption, there is still no comparator suitable for GS/s applications in related document.
Regarding a background offset calibration technique applied for the dynamic comparator, that could be used to improve the accuracy of comparator to achieve the requirements of medium/high resolution of the comparator based ADCs. A popular structure is to apply two independent comparators in collaboration with a same control clock signal is generally used. Moreover, during a disable phase of a previous clock cycle of the control clock signal, the two comparators are all reset, and during an enable phase of the previous clock cycle, one of the comparators performs the comparison of the input refer offset, and another comparator performs the comparison of a differential input signal. Thereafter, during a disable phase of a current clock cycle of the control clock signal, the two comparators are still reset, though during an enable phase of the current clock cycle, the comparator previously used for performing the comparison of the input refer offset is now used for performing the comparison of the differential input signal, while the comparator previously used for performing the comparison of the differential input signal is now used for performing the comparison of the input refer offset. In other words, the conventional control clock signal is used to control operations of the two independent comparators in a time-interleaved approach, so as to implement a background offset calibration mechanism of the dynamic comparator.